Conventional very large scale integrated (VLSI) circuits may contain thousands or millions of transistors, registers, latches, and flip-flops which store state information. These circuit elements must be properly initialized or reset prior to functional operation. Initialization is often performed by means of a power up reset signal.
A power up reset signal is a digital signal that is asserted while external power is being applied to a chip or integrated circuit. The power up reset signal drives the set or reset inputs of, for example, flip-flops to initialize the state of the integrated circuit to a predefined and known condition. After a suitable delay after the application of the external power to the integrated circuit, the power up reset signal is de-asserted.
It is desirable for a power up reset circuit to dissipate low amounts of static or direct current (DC) power when an integrated circuit is operating. The power up reset circuit is active only for a brief period of time when power is first applied to the integrated circuit. Therefore, any power dissipated by the power up reset circuit at any other time when the integrated circuit is functioning is wasted power. This may undesirably run down the battery of a system that includes the power up reset circuit. Reset signal generating circuits disclosed in U.S. Pat. No. 4,607,178 and U.S. Pat. No. 4,902,907 suffer from this problem.
It is also desirable for a power up reset circuit to function correctly at low operating voltages. Integrated circuits are being required to function at lower and lower supply voltages. For integrated circuits that are manufactured from complementary metal oxide semiconductor (CMOS) process technologies, low power supply voltages typically result in lower power dissipation and higher speed circuits due to shorter channel lengths and thinner oxides. It is highly desirable for a CMOS power up reset circuit to function correctly when the power supply voltage (VDD) is approximately twice the absolute value of the threshold voltage (VT) of one of the NMOS or PMOS transistors. The power up reset circuits disclosed in U.S. Pat. No. 4,591,745, U.S. Pat. No. 4,591,745, and U.S. Pat. No. 4,970,408 do not function properly when their power supply voltage are only slightly above twice the absolute threshold voltage of their NMOS or PMOS transistors.
It is also desirable for a power up reset circuit to generate a power up reset signal having a guaranteed minimum pulse width (active or assertion time). If there is a known, guaranteed, minimum time during which the power up reset signal is active, state bits may be set or cleared during this time. Therefore, a guaranteed minimum reset power up signal pulse width facilitates the design of state flip-flops and finite state machines which use the power up reset signal. Power up reset circuits disclosed in U.S. Pat. No. 4,210,829, U.S. Pat. No. 4,970,408, and U.S. Pat. No. 5,323,067 do not generate a power up reset signal having a guaranteed pulse width.